Semiconductor integrated circuit

ABSTRACT

A semiconductor integrated circuit includes a bridge circuit which controls a data transfer of a bus line, peripheral circuits which are connected to the bridge circuit through the busline, and a control circuit which is formed at the peripheral circuits. The control circuit receives a select signal and controls the data transfer in the peripheral circuits in accordance with a logic state of the select signal.

CROSS REFERENCE TO RELATED APPLICATION

[0001] The present application claims priority under 35 U.S.C. § 119 toJapanese Patent Application No. 2001-196320, filed Jun. 28, 2001, whichis herein incorporated by reference in its entirely for all purposes.

BACKGROUND OF THE INVENTION

[0002] 1. Field of the Invention

[0003] The present invention relates to a semiconductor integratedcircuit, and more particularly to the layout of peripheral circuitswhich one connected to an address bus.

[0004] 2. Description of the Related Art

[0005] A system large scale integrated circuit (a system LSI) is knownas a conventional semiconductor integrated circuit. In a system LSI, aplurality of peripheral circuits are electrically connected to a centralprocessing unit (CPU) through a common address bus, so as to reduce alayout area of the bus configuration in the system LSI.

[0006] In a common address bus configuration, an address signal iscommunicated to both an accesses peripheral circuit and non-accessedperipheral circuits. As a result, a current flows in a circuit portionof the non-accessed peripheral circuits, for example, a write resisterand a read resister. Accordingly, unnecessary power consumption occursin the non-accessed circuits.

[0007] Recently, with the enhancement of the integration level of thesystem LSI, the number of the peripheral circuits included in the systemLSI has increased, and accordingly, the unnecessary power consumption ofthe non-accessed peripheral circuits has increased. Further, since thenumber of the peripheral circuits has increased, it is desired to reducethe layout area of the address bus on the system LSI.

SUMMARY OF THE INVENTION

[0008] In a semiconductor integrated circuit according to the presentinvention, a bridge circuit controls a data transfer of the bus, aplurality of peripheral circuits are connected to the bridge circuitthrough the bus, and a control circuit is formed in the peripheralcircuits. The control circuit receives a select signal and controls thedata transfer in the peripheral circuits in accordance with a logicstate of the select signal.

[0009] The present invention can reduce a power consumption of anon-accessed address bus. Further, the present invention can reduce alayout area of the address bus.

[0010] The above and further objects and novel features of the inventionwill become more fully apparent from the following detailed description,appended claims and accompanying drawings herein.

BRIEF DESCRIPTION OF THE DRAWINGS

[0011] While the specification concludes with claims particularlypointing out and distinctly claiming the subject matter which isregarded as the invention, it is believed that the invention, theobjects and features of the invention and further objects, features andadvantages thereof will be better understood from the followingdescription taken in connection with the accompanying drawings in which:

[0012]FIG. 1 is a block diagram of a semiconductor integrated circuitaccording to a first preferred embodiment of the present invention;

[0013]FIG. 2 is a signal timing chart of the semiconductor integratedcircuit according to the first preferred embodiment of the presentinvention;

[0014]FIG. 3 is a block diagram of a semiconductor integrated circuitaccording to a second preferred embodiment of the present invention;

[0015]FIG. 4 is a signal timing chart of the semiconductor integratedcircuit according to the second preferred embodiment of the presentinvention;

[0016]FIG. 5 is a block diagram of a semiconductor integrated circuitaccording to a third preferred embodiment of the present invention;

[0017]FIG. 6 is a block diagram of a semiconductor integrated circuitaccording to a fourth preferred embodiment of the present invention;

[0018]FIG. 7 is a block diagram of a semiconductor integrated circuitaccording to a fifth preferred embodiment of the present invention;

[0019]FIG. 8 is a block diagram of a semiconductor integrated circuitaccording to a sixth preferred embodiment of the present invention; and

[0020]FIG. 9 is a block diagram of a semiconductor integrated circuitaccording to a seventh preferred embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0021] Preferred embodiments of the present invention will hereinafterbe described in detail with reference to the accompanying drawings. Thedrawings used for this description typically illustrate majorcharacteristic parts to facilitate understanding of the invention.

[0022]FIG. 1 is a block diagram of a semiconductor integrated circuitaccording to a first preferred embodiment of the present invention, andin particular, FIG. 1 shows a peripheral circuit 11. The peripheralcircuit 11 includes an AND gate 13 which receives an input addresssignal IAS and a select signal S, and a logic circuit 14 which receivesan output of the AND gate 13. The AND gate 13 has two input terminals.One of the input terminals is electrically connected to an address bus12 and the other one is electrically connected to a select signal line20. The AND gate 13 transfers the input address signal IAS outputtedfrom a CPU to the logic circuit 14 as an output address signal OAS, whenthe select signal S is an active state. The logic circuit 14 isconsisted of, for example, a write resister and a read resister.

[0023]FIG. 2 is a signal timing chart of the semiconductor integratedcircuit according to the first preferred embodiment of the presentinvention. Specifically, FIG. 2 shows the input address signal IAS, theselect signal S and the output address signal OAS. As shown in FIG. 2,when an address of the peripheral circuit 11 is “3”, the AND gate 13receives the input address signal IAS having an address “3” which is thesame as the address “3” of the peripheral circuit 11, and outputs theoutput address signal OAS having an address “3”, to the logic circuit14, when the select signal S is an active state. At that time, a voltageof the output address signal OAS having the address “3” is, for example,5V.

[0024] On the other hand, the AND gate 13 outputs the output addresssignal OAS having an address “0” when the select signal is an inactivestate. The output address signal OAS having the address “0” indicates,for example, that a voltage of all signal lines of the address bus 12 is0V.

[0025] According to the first preferred embodiment of the presentinvention, since the output address signal OAS which is applied to theperipheral circuit 14 can be kept at 0V when the peripheral circuit 11is a non-accessed state, the application of a voltage to the logiccircuit 14 can be inhibited. Therefore, a power consumption of thenon-accessed peripheral circuit can be reduced.

[0026]FIG. 3 is a block diagram of a semiconductor integrated circuitaccording to a second preferred embodiment of the present invention, andin particular, FIG. 3 shows a peripheral circuit 111. The peripheralcircuit 111 includes an latch circuit 15 which receives an input addresssignal IAS and receives a select signal S as a gate signal, and a logiccircuit 14 which receives an output of the latch circuit 15. The latchcircuit 15 has a data input terminal D and a gate terminal G. The datainput terminal D is electrically connected to an address bus 12, and thegate terminal G is electrically connected to a select signal line 20.The latch circuit 15 receives and holds an address of the input addresssignal IAS outputted from a CPU when the select signal S is an activestate, and outputs the address to the logic circuit 14 as an outputaddress signal OAS. The logic circuit 14 is consisted of, for example, awrite resister and a read resister.

[0027]FIG. 4 is a signal timing chart of the semiconductor integratedcircuit according to the second preferred embodiment of the presentinvention. Similar to the first preferred embodiment, FIG. 4 shows theinput address signal IAS, the select signal S and the output addresssignal OAS. As shown in FIG. 4, when the address of the peripheralcircuit 111 is “3”, the latch circuit 15 receives and holds the inputaddress signal IAS having the address “3” which is the same as theaddress “3” of the peripheral circuit 111, and continues to output theoutput address signal OAS having the address “3” to the logic circuit14, after when the select signal S changes an active state. At thattime, a voltage of the output address signal OAS having the address “3”is, for example, 5V.

[0028] On the other hand, the latch circuit 15 outputs the outputaddress signal OAS having an address “0” when the select signal is aninactive state. The output address signal OAS having the address “0”indicates, for example, that a voltage of all signal lines of theaddress bus 12 is 0V.

[0029] According to the second preferred embodiment of the presentinvention, since the output address signal OAS which is applied to theperipheral circuit 14 can be held to 0V when the peripheral circuit 11is in a non-accessed state, the application of a voltage to the logiccircuit 14 can be inhibited. Therefore, power consumption of thenon-accessed peripheral circuit can be reduced.

[0030]FIG. 5 is a block diagram of a semiconductor integrated circuitaccording to a third preferred embodiment of the present invention. Inthe third preferred embodiment, gates G1 through G5 are formedexternally of peripheral circuits P1 through P5, while the gate (e.g.,the AND gate 13 and the latch circuit 15) is formed in the peripheralcircuit 11 and 111, in the first and second preferred embodiments.

[0031] As shown in FIG. 5, a main address bus 12 a extending from abridge circuit 9 branches off into five branch address buses 12 b, andthe five branch buses 12 b are electrically connected to the fiveperipheral circuits P1 through P5, respectively. The gates G1 through G5are formed at locations just after the main address bus 12 a is branchedoff into the branch address buses 12 b. Each branch address bus 12 bincludes sub-buses 12 b 1 and 12 b 2. The sub-bus 12 b 2 is longer thanthe sub-bus 12 b 1. Select signals S1 through S5 are applied to thegates G1 through G5, respectively. As a result, an opened and closedstate of the gates G1 through G5 are controlled in accordance withstates (active and inactive) of the select signals S1 through S5. Inthis way, an address signal on the main address bus 12 a is notcommunicated to the branch address bus 12 b connected to a non-accessedperipheral circuit.

[0032] According to the third preferred embodiment of the presentinvention, since a voltage of all signal lines of the branch address bus12 b which are not communicated with the address signal on the mainaddress bus 12 a is held to 0V, current does not flow to these signallines. Therefore, a power consumption of the non-accessed peripheralcircuits can be reduced.

[0033]FIG. 6 is a block diagram of a semiconductor integrated circuitaccording to a fourth preferred embodiment of the present invention. Asshown in FIG. 6, gates G1 through G5 are formed externally of peripheralcircuits P1 through P5, and a gate G6 is formed in a main bus 12 a. Thegate G6 is, for example, an AND gate or a latch circuit, and transfer anaddress signal when an output of a select circuit 16 is an active state.The select circuit 16 is, for example, an OR gate.

[0034] The main address bus 12 a extending from a bridge circuit 9branches off into five branch address buses 12 b, and the five branchbuses 12 b are electrically connected to the five peripheral circuits P1through P5, respectively. The gates G1 through G5 are formed and locatedjust after the main address bus 12 a is branched off into the branchaddress buses 12 b. The branch address bus 12 b includes sub-buses 12 b1 and 12 b 2. The sub-bus 12 b 2 is longer than the sub-bus 12 b 1.Select signals S1 through S5 are applied to the gates G1 through G5,respectively. Also, select signals S3 through S5 are applied to theselect circuit 16. The select circuit 16 simply selects and outputs theselect signal S3 through S5 for the peripheral circuit P3 through P5which are located after the gate G6. As a result, the gate G6 transfersthe address signal when one of the peripheral circuits P3 through P5 areaccessed. However, the gate G6 does not transfer the address signal whenthe peripheral circuits P1 and P2 are accessed. Therefore, a voltage ofall signal lines of the main address bus 12 a locating at an output sideof the gate G6 is fixed at 0V. The gate G6 can be controlled by anexclusive decode signal in place of the output of the select circuit 16.

[0035] According to the fourth preferred embodiment of the presentinvention, since the voltage of all signal lines of the main address bus12 a located at the output side of the gate G6 is fixed to 0V when theperipheral circuits P3 through P5 located at outside of the gate G6 arenon-accessed, a useless current does not flow to the all signal lines ofthe main address bus 12 a located at the output side of the gate G6.Therefore, a power consumption of the non-accessed peripheral circuitscan be reduced.

[0036]FIG. 7 is a block diagram of a semiconductor integrated circuitaccording to a fifth preferred embodiment of the present invention. Asshown in FIG. 7, a main address bus 12 a extending from a bridge circuit9 is divided into two routes A and B by a distributing circuit 17.Similar to the fourth and fifth preferred embodiments, a branch addressbus 12 b includes sub-buses 12 b 1 and 12 b 2. The sub-bus 12 b 2 islonger than the sub-bus 12 b 1. The distributing circuit 18 includes agate G7 which is formed on the route A, a gate G8 which is formed on theroute B, a select circuit 18 which is electrically connected to an inputof the gate G7, and a select circuit 19 which is electrically connectedto an input of the gate G8. The gate G7 transfers an address signal whenan output of the select signal 18 is an active state. The gate G8transfers the address signal when an output of the select circuit 19 isan active.

[0037] The select circuit 18 receives select signals S1 and S2 forperipheral circuits P1 and P2 which are electrically connected to branchbuses branching from the route A. Therefore, the gate G7 transfers theaddress signal when one of the peripheral circuits P1 and P2 isaccessed. However, when the peripheral circuits P1 and P2 arenon-accessed, a voltage of all signal lines of the route A is fixed at0V.

[0038] The select circuit 19 receives select signals S3 through S5 forperipheral circuits P3 through P5 which are electrically connected tobranch buses branching from the route B. Therefore, the gate G8tarnsfers the address signal when one of the peripheral circuits P3through P5 is accessed. However, when the peripheral circuits P3 throughP5 are non-accessed, a voltage of all signal lines of the route B isfixed at 0V.

[0039] According to the fifth preferred embodiment of the presentinvention, since the main address bus is divided into the plurality ofthe routes A and B, all routes without the route leading to the accessedperipheral circuit are an inactive state. Therefore, a power consumptionof the non-accessed peripheral circuits can be reduced.

[0040]FIG. 8 is a block diagram of a semiconductor integrated circuitaccording to a sixth preferred embodiment of the present invention.Peripheral circuits P1 through P5 have various resisters. A number ofsignal lines of an address bus leading to the peripheral circuits P1through P5 is decided according to a number of the resisters beingsubject to access. A number of signal lines of the address bus indicatesa number of bits of the address bus. Specifically, when the peripheralcircuit P1 has the most resisters being subject to access, a number ofbits of the address bus leading to the peripheral circuit P1 is themost. On the other hand, when the peripheral circuit P5 has the fewestresisters being subject to access, a number of bits of the address busleading to the peripheral circuit P5 is the fewest. At that time, anumber of the signal lines of the address bus indicates a width of theaddress bus. Therefore, when the peripheral circuit P1 has the mostresisters being subject to access, the address bus leading to theperipheral circuit P1 is the widest. On the other hand, when theperipheral circuit P5 has the fewest resisters being subject to access,the address bus leading to the peripheral circuit P5 is the most narrow.

[0041] The peripheral circuit P1 is located closest to the bridgecircuit 9, and the peripheral circuit P5 is located farthest from thebridge circuit 9. Therefore, a number of bits of the address bus leadingto the peripheral circuit P1 is the most. On the other hand, a number ofbits of the address bus leading to the peripheral circuit P5 is thefewest. A number of bits of the address bus indicates a width of theaddress bus. Therefore, the address bus leading to the peripheralcircuit P1 is the widest. On the other hand, the address bus leading tothe peripheral circuit P5 is the most narrow.

[0042] As shown in FIG. 8, the address bus leading to the peripheralcircuit P1 which is located closest to a bridge circuit 9 is consistedof five signal lines. The address bus leading to a peripheral circuit P2is consisted of three signal lines. The address buses leading toperipheral circuits P3 and P4 are consisted of two signal lines. Theaddress bus leading to the peripheral circuit P5 which is located at thefarthest from the bridge circuit 9 is consisted of one signal line.

[0043] Specifically, the address bus having five signal lines areelectrically connected to a gate G1. Also, three signal lines of theaddress bus having five signal lines are electrically connected to agate G2. Two signal lines of the address bus having five signal linesare electrically connected to a gate G6. The two signal lines connectingto the gate G6 are electrically connected to gates G3 and G4. One of thetwo signal lines connecting to the gate G6 is electrically connected toa gate G5.

[0044] According to the sixth preferred embodiment of the presentinvention, since a layout area of the address bus can be reduced, apower consumption of the address bus can be reduced.

[0045]FIG. 9 is a block diagram of a semiconductor integrated circuitaccording to a seventh preferred embodiment of the present invention. Asshown in FIG. 9, an address bus leading to a peripheral circuit P3 whichis located closest to a bridge circuit 9 is consisted of five signallines. The address buses leading to peripheral circuits P1 and P4 areconsisted of three signal lines. In a route A, the address bus leadingto the peripheral circuit P2 which is located farthest from the bridgecircuit 9 is consisted of one signal line. Similarly, in a route B, theaddress bus leading to the peripheral circuit P5 which is locatedfarthest from the bridge circuit 9 is consisted of one signal line.Therefore, a number of bits of the address bus leading to the peripheralcircuit P3 is the most. On the other, hand, in the route A, a number ofbits of the address bus leading to the peripheral circuit P2 is thefewest. In the route B, a number of bits of the address bus leading tothe peripheral circuit P5 is the fewest. A number of bits of the addressbus indicates a width of the address bus. Therefore, the address busleading to the peripheral circuit P3 is the widest. On the other hand,in the route A, the address bus leading to the peripheral circuit P2 isthe most narrow. And, in the route B, the address bus leading to theperipheral circuit P5 is the most narrow.

[0046] Specifically, the address bus having five signal lines iselectrically connected to a gate G8. Three signal lines of the addressbus having five signal lines are electrically connected to a gate G7.The five signal lines connected to G8 are electrically connected to agate G3 Three signal lines of the five signal lines connected to thegate G8 are electrically connected to gates G4. One of the five signallines connected to the gate G8 is electrically connected to a gate G5.The three signal lines connected to the gate G7 are electricallyconnected to gates G1. One of the three signal lines connected to thegate G7 is electrically connected to a gate G2.

[0047] According to the seventh preferred embodiment of the presentinvention, since a layout area of the address bus can be reduced, apower consumption of the address bus can be reduced.

[0048] While the present invention present an example in which powerconsumption of the address bus is reduced, the invention is not limitedto this example and may be used to reduce the power consumption of adata bus.

[0049] As described above, according to the semiconductor integratedcircuit of the present invention, a power consumption of a non-accessedaddress bus can be reduced. Further, a layout area of the address buscan be reduced.

[0050] The present invention has been described with reference toillustrative embodiments, however, this description must not beconsidered to be confined only to the embodiments illustrated. Variousmodifications and changes of these illustrative embodiments and theother embodiments of the present invention will become apparent to oneskilled in the art from reference to the description of the presentinvention. It is therefore contemplated that the appended claims willcover any such modifications or embodiments as fall within the truescope of the invention.

What is claimed is:
 1. A semiconductor integrated circuit, comprising: abus line; a plurality of peripheral circuits which are connected to thebus line; a bridge circuit which is connected to the bus line and whichcontrols a data transfer over the bus line to the plurality of theperipheral circuits; a plurality of control circuits which connectedbetween the bus line and the peripheral circuits, respectively, whereineach control circuit receives a select signal and controls the datatransfer to a respective the peripheral circuit in accordance with alogic state of the select signal.
 2. The semiconductor integratedcircuit according to claim 1, wherein the control circuit includes anAND circuit.
 3. The semiconductor integrated circuit according to claim1, wherein the control circuit includes a latch circuit.
 4. Asemiconductor integrated circuit, comprising: a bridge circuit whichcontrols a data transfer of a bus line, wherein the bus line includes amain bus line connected to the bridge circuit, a first branch bus lineconnected to the main bus line, and a second branch bus line which islonger than the first branch bus line; a control circuit, connectedbetween the first and second branch bus lines, which receives a selectsignal and transfers a data from the first branch bus line to the secondbranch bus line in accordance with a logic state of the select signal;and a peripheral circuit which is connected to the second branch busline.
 5. The semiconductor integrated circuit according to claim 4,wherein the control circuit includes an AND circuit.
 6. Thesemiconductor integrated circuit according to claim 4, wherein thecontrol circuit includes a latch circuit.
 7. A semiconductor integratedcircuit, comprising: a bridge circuit which controls a data transfer ofa bus line, wherein the bus line includes first and second main buslines connected to the bridge circuit, a first branch bus line connectedto the first main bus line, and a second branch bus line connected thesecond main bus line; a first control circuit, connected between thefirst and second main bus lines, which receives a select signal andtransfers a data from the first main bus line to the second main busline in accordance with a logic state of the select signal; and aplurality of peripheral circuits which are connected to the first andsecond branch bus lines.
 8. The semiconductor integrated circuitaccording to claim 7, wherein the first control circuit includes an ANDcircuit.
 9. The semiconductor integrated circuit according to claim 7,wherein the first control circuit includes a latch circuit.
 10. Thesemiconductor integrated circuit according to claim 7, furthercomprising: a second control circuit which is formed between the firstand second main bus lines and the peripheral circuits, and which islocated at the first and second branch bus lines.
 11. The semiconductorintegrated circuit according to claim 10, wherein the second controlcircuit includes an AND circuit.
 12. The semiconductor integratedcircuit according to claim 10, wherein the second control circuitincludes a latch circuit.
 13. The semiconductor integrated circuitaccording to claim 10, wherein the first and second branch bus lineshave a plurality of first sub-bus lines located between the first mainbus line and the second control circuit, and a plurality of secondsub-bus lines located between the second main bus line and the secondcontrol circuit, and wherein the second sub-bus line is longer than thefirst sub-bus line.
 14. The semiconductor integrated circuit accordingto claim 13, wherein the second sub-bus line leaded to a one of theperipheral circuits which is located closest to the bridge circuit isthe widest, and wherein a one of the second sub-bus lines leading to aone of the peripheral circuits which is located farthest from the bridgecircuit is the most narrow.
 15. The semiconductor integrated circuitaccording to claim 13, wherein a number of bits of a one of the secondsub-bus lines leading to a one of the peripheral circuits which islocated closest to the bridge circuit is the most, and wherein a numberof bits of a one of the second sub-bus lines leading to a one of theperipheral circuits which is located farthest from the bridge circuit isthe fewest.
 16. A semiconductor integrated circuit having a bus,comprising: a bridge circuit which controls a data transfer of a busline, wherein the bus line includes first and second main bus linesconnected to the bridge circuit, a first branch bus line connected tothe first main bus line, and a second branch bus line connected to thesecond main bus line; a first control circuit, connected between thebridge circuit and the first and second main bus line, which receives aselect signal and transfers a data outputted from the bridge circuit toone of the first and second main bus lines in accordance with a logicstate of the select signal; and a plurality of peripheral circuits whichare connected to the first and second branch bus lines.
 17. Thesemiconductor integrated circuit according to claim 16, furthercomprising: a second control circuit which is connected between thefirst main bus line and the peripheral circuits, and which is located atthe first branch bus line; and a third control circuit which isconnected between the second main bus line and the peripheral circuits,and which is located at the second branch bus line.
 18. Thesemiconductor integrated circuit according to claim 17, wherein thesecond and third control circuits are AND circuits.
 19. Thesemiconductor integrated circuit according to claim 17, wherein thesecond and third control circuits are latch circuits.
 20. Thesemiconductor integrated circuit according to claim 16, wherein thefirst and second branch bus lines have a first sub-bus line locatedbetween the first main bus line and the second control circuit, and asecond sub-bus line located between the second control circuit and theperipheral circuit, and a third sub-bus line located between the secondmain bus line and the third control circuit, and a fourth sub-bus linelocated between the third control circuit and the peripheral circuit,and wherein the second sub-bus line is longer than the first sub-busline and the fourth sub-bus line is longer than the third sub-bus line.21. The semiconductor integrated circuit according to claim 20, whereinthe second sub-bus line leading to a one of the peripheral circuitswhich is located closest to the bridge circuit is the widest, and thesecond sub-bus line leading to a one of the peripheral circuits which islocated farthest from the bridge circuit is the most narrow, and whereinthe fourth sub-bus line leading to a one of the peripheral circuitswhich is located closest to the bridge circuit is the widest, and thefourth sub-bus line leading to a one of the peripheral circuits which islocated at the farthest to the bridge circuit is the most narrow. 22.The semiconductor integrated circuit according to claim 20, wherein anumber of bits of the second sub-bus line leading to a one of theperipheral circuits which is located closest to the bridge circuit isthe most, and a number of bits of the second sub-bus line leading to aone of the peripheral circuits which is located at the farthest to thebridge circuit is the fewest, and wherein a number of bits of the fourthsub-bus line leading to a one of the peripheral circuits which islocated closest to the bridge circuit is the most, and a number of bitsof the fourth sub-bus line leading to a one of the peripheral circuitswhich is located at the farthest to the bridge circuit is the fewest.